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rev c data sheet no. pd60312 b 1/ 02 /2014 irmcf311 dual c hannel sensorless motor control ic for appliance s features ? mce tm ( motion control engine) - hardware based computation engine for high efficiency sinusoidal s ensorless control of permanent magnet ac motor ? integrated p ower f actor c orrection control ? support s both interior and surface permanent magnet motor s ? built - in hardware peripheral for single shunt current feedback reconstruction ? no external current or voltage sensin g operational amplifier required ? dual channel three/two - phase space vector pwm ? t wo - channel analog output (pwm) ? embedded 8 - bit high speed microcontroller (8051) for flexible i/o and man - machine control ? jtag programming port for emulation/debugger ? two serial communication interface (uart) ? i 2 c /spi serial interface ? watchdog timer with independent analog clock ? three general purpose t imer s ? t wo special t imer s: periodic timer, capture timer ? external eeprom and internal ram facilitate debugging and code development ? pin compatible with irmck3 11, otp - rom version ? 1.8v/3.3v cmos product summary maximum crystal frequency 60 mhz maximum internal clock (sysclk) frequency 128 mhz sensorless control computation time 11 sec typ mce tm computation data range 16 bit signed program ram loaded from external eeprom 48k byte s data ram 8 k byte s gatekill latency (digital filtered) 2 sec pwm carrier frequency counter 16 bits/ sysclk a/d input channels 6 a/d converter resolution 1 2 bits a/d converter conversion speed 2 sec 8051 instruction execution speed 2 sysclk analog output (pwm) resolution 8 bit s uart baud rate (typ) 57.6k bps number of i/o (max) 14 package (lead - free) qfp 64 description irmcf311 is a high performance ram based motion control ic designed primarily for appliance application s . irmcf311 is designed to achieve low cost and high performance control solution s for advanced inverterized appliance motor control. irmcf311 contains two computation engines. one is motion control engine (mce tm ) for sensorless control of permanent magnet motor s ; the other is an 8 - bit high - speed microcontroller (8051). both computation engi nes are integrated into one monolithic chip. the mce tm contains a collection of control elements such as proportional plus integral, vector rotator, angle estimator, multiply/divide, low loss svpwm, single shunt ifb. the user can program a motion control a lgorithm by connecting these control elements using a graphic compiler. key components of the sensorless control algorithm s, such as the angle estimator, are provided as complete pre - defined control blocks implemented in hardware . a unique analog/digital c ircuit and algorithm to fully support single shunt current reconstruction is also provided. the 8051 microcontroller performs 2 - cycle instruction execution (60mips at 120mhz). the mce and 8051 microcontroller are connected via dual port ram to process sign al monitoring and command input . an a dvanced graphic compiler for the mce tm is seamlessly integrated in to the matlab /simulink environment, while third party jtag based emulator tools are supported for 8051 developments . irmcf311 comes with a small qfp 64 pi n lead - free package.
irmcf311 2 table of contents 1 overview ...................................................................................................................................... 4 2 irmcf311 block diagram and main functions ......................................................................... 5 3 pin out ........................................................................................................................................... 7 4 input/output of irmcf311 ......................................................................................................... 8 4.1 8051 peripheral interface group ........................................................................................... 8 4.2 motion peripheral interface group ....................................................................................... 9 4.3 analog interface group ....................................................................................................... 10 4.4 power interf ace group ........................................................................................................ 11 4.5 test interface group ............................................................................................................ 11 5 application connections ........................................................................................................... 12 6 dc characteristics ..................................................................................................................... 13 6.1 absolute maximum ratings ............................................................................................... 13 6.2 system clock frequency and power consumption ............................................................ 13 6.3 digital i/o dc characteristics ............................................................................................ 14 6.4 pll and oscillator dc characteristics ............................................................................... 15 6.5 analog i/o dc characteristics ........................................................................................... 15 6.6 analog i/o dc characteristics ........................................................................................... 16 6.7 under voltage lockout dc characteristics ........................................................................ 17 6.8 cmext and aref characteristics .................................................................................... 17 7 ac characteristics ..................................................................................................................... 18 7.1 pll ac characteristics ...................................................................................................... 18 7.2 analog to digital converter ac characteristics ................................................................. 19 7.3 op amp ac characteristics ................................................................................................. 20 7.4 op amp ac characteristics ................................................................................................ 20 7.5 sync to svpwm and a/d conversion ac timing ......................................................... 21 7.6 gatekill to svpwm ac timing .................................................................................. 22 7.7 interrupt ac timing ........................................................................................................... 22 7.8 i 2 c ac timing .................................................................................................................... 23 7.9 spi ac timing .................................................................................................................... 24 7.9.1 spi write ac timing .................................................................................................... 24 7.9.2 spi read ac timing .................................................................................................... 25 7.10 uart ac timing ........................................................................................................... 26 7.11 capture input ac timing .......................................................................................... 27 7.12 jtag ac timing ............................................................................................................ 28 8 i/o structure .............................................................................................................................. 29 9 pin list ....................................................................................................................................... 32 10 package dimensions ............................................................................................................... 35 11 part marking information ....................................................................................................... 36
irmcf311 3 table of figures figure 1. typical application block diagram using irmcf311 .................................................. 4 figure 2. irmcf311 internal block diagram ................................................................................. 5 figure 3. irmcf311 pin configuration .......................................................................................... 7 figure 4. input/output of irmcf311 ............................................................................................. 8 figure 5. application connection of irmcf311 .......................................................................... 12 figure 6. clock frequency vs. power consumption ..................................................................... 13 figure 7 al l digital i/o and pwm outputs .................................................................................... 29 figure 8 reset, gatekill i/o ................................................................................................. 29 figure 9 analog input .................................................................................................................... 30 figure 10 analog operational amplifier output and aref i/o structure ...................................... 30 figure 11 vss, avss and pllvss pin structure ........................................................................ 30 figure 12 vdd1, vdd2, avdd and pllvdd pin structure ..................................................... 31 figure 13 xtal0/xtal1 pins structure ...................................................................................... 31 table of tables table 1. absolute maximum ratings ............................................................................................ 13 table 2. system clock frequency ................................................................................................. 13 table 3. digital i/o dc characteristics ........................................................................................ 14 table 4. pll dc characteristics ................................................................................................... 15 table 5. analog i/o dc characterist ics ........................................................................................ 15 table 6. analog i/o dc characteristics ........................................................................................ 16 table 7. uvcc dc characteristics ................................................................................................ 17 table 8. cmext and aref dc characteristics .......................................................................... 17 table 9. pll ac characteristics ................................................................................................... 18 table 10. a/d convert er ac characteristics ................................................................................ 19 table 11. current sensing op amp ac characteristics ............................................................... 20 table 12. voltage sensing op amp ac characteri stics ............................................................... 20 table 13. sync ac characteristics ............................................................................................. 21 table 14. gatekill to svpwm ac timing ............................................................................ 22 table 15. interrupt ac timing ...................................................................................................... 22 table 16. i 2 c ac timing .............................................................................................................. 23 table 17. spi write ac timing .................................................................................................... 24 table 18. spi read ac timing ..................................................................................................... 25 table 19. uart ac timing ......................................................................................................... 26 table 20. capture ac timing ................................................................................................. 27 table 21. jtag ac timing .......................................................................................................... 28 table 22. pin list .......................................................................................................................... 34
irmcf311 4 overview irmcf311 is a new international rectifier integrated circuit device primarily designed as a one - chip solution for complete inverter controlled air conditioner motor control application s . unlik e a traditional microcontroller or dsp, the irmcf311 provides a built - in closed loop sensorless control algorithm using the unique motion control engine (mce tm ) for permanent magnet motor s . the mce tm consists of a collection of control elements, motion per ipherals, a dedicated motion control sequencer and dual port ram to map internal signal nodes. irmcf311 also employs a unique single shunt current reconstruction circuit to eliminate additional analog/digital circuit ry and enables a direct shunt resistor i nterface to the ic. motion control programming is achieved using a dedicated graphical compiler integrated into the matlab /simulink tm development environment . sequencing, user interface, host communication, and upper layer control tasks can be implemented in the 8051 high - speed 8- bit microcontroller. the 8051 microcontroller is equipped with a jtag port to facilitate emulation and debugging tools. figure 1 shows a typical application schematics using irmcf311. irm cf3 11 is intended for development purpose and contains 48k byte s of ram, which can be loaded from external eeprom for 8051 program execution. for high volume production, irmck311 contains otp rom in place of program ram to reduce the cost. both irmc f 311 an d irmc k 311 come in the same 64- pin qf p package with identical pin configuration to facilitate pc board layout and transition to mass production passive emi filter irmcf 311 galvanic isolation ir s 2630d ipm dc bus communication to indoor unit ac input (100- 230v) compressor motor spm ir s 2631d 60-100w fan motor igbt inverter fredfet inveter eeprom 7 6 2 user parameter storage analog output digital i/o 2 1 3 temperature feedback analog actuators relay, valves, switches motor pwm + pfc+gf fault eeprom user program storage analog input galvanic isolation field service fault rs232c serial comm temp sense multple power supply motor pwm 15v 3.3v 1.8v figure 1 . typical application block diagram using irm cf311
irmcf311 5 2 irmcf311 block d iagram and main functions irmcf311 block diagram is shown in figure 2. 8bit cpu core motion control sequencer motion control modules dual port ram 512 bytes * mce program ram 5.5kbytes* local ram 2kbytes * program ram 48kbytes 8bit up address/data bus motion control bus a/d mux s/h & op amp d/a (pwm) timer counnter0 watchdog timer uart0 port 1 6 dual channel low loss svpwm ac line volt sensing cgatekill to motor1 igbt gate drive mce ( motion control engine) monitoring host interface digital i/os 8051 microcontroller ain0 jtag emulator debugger 4 pll 2 crystal (4mhz) 120mhz analog inputs (2) ain1 port 2 port 3 3 timer counnter1 timer counnter2 periodic timer interrupt control pfc pwm to pfc igbt gate drive pfcgkill single shunt current sensing motor1 shunt resistor uart1 port 5 6 fgatekill to motor2 igbt gate drive 3 motor2 shunt resistor 3 i2c / spi eeprom interface * sizes are configurable dc bus volt sensing 3 (4) (4) (4) 2 2 2/4 pfc current sensing 3 figure 2 . irmcf311 internal block diagram irmcf311 contai ns the following functions for sensorless ac motor control applications: ? motion control engine (mce tm ) o proportional plus integral block o low pass filter o differentiator and lag (high pass filter) o ramp o limit o angle estimate (sensorless control) o inverse clark transformation o vector rotator o bit latch
irmcf311 6 o peak detect o transition o mu l tiply - divide (signed and unsigned) o divide (signed and unsigned) o adder o subtractor o comparator o counter o accumulator o switch o shift o atan (arc tangent) o function block (any curve fitting, nonlinear f unction) o 16- bit wide logic operation s (and, or, xor , not, negate) o mce tm program and data memory ( 6k byte) . note 1 o mce tm control sequencer ? 8051 microcontroller o three 16 - bit timer o 16- bit periodic timer o 16- bit analog watchdog timer o 16- bit capture timer o up to 14 dis crete i/os o six - channel 12- bit a/d ? four b uffered channel s (0 ? 1.2v input) ? two u nbuffered channels (0 ? 1.2v input) o jtag port (4 pins) o up to two channels of analog output (8- bit pwm) o two uart o i 2 c /spi port o 48 k byte program ram loaded from external eep rom o 2k byte data ram . note 1 note 1: total size of ram is 8k byte including mce program, mce data, and 8051 data. different sizes can be allocated depending on applications.
irmcf311 7 3 pin out 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 15 14 13 16 3 12 4 11 5 6 7 8 9 10 2 1 xtal 0 xtal 1 p 1 . 1 / rxd p 1 . 2 / txd vdd 1 vss vdd 2 p 1 . 3 / sync / sck p 1 . 4 / cap p 3 . 6 / rxd 1 p 3 . 7 / txd 1 fpwmvl fpwmul 34 35 36 33 46 37 45 38 44 43 42 41 40 39 47 48 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 vss vdd 2 avdd avss ain 0 aref p 2 . 7 / aopwm 1 p 2 . 6 / aopwm 0 cpwmuh cpwmvh cpwmwh cpwmul cpwmvl cpwmwl cgatekill vdd 1 vss ifbco ifbc + ifbc - pllvss pllvdd reset tstmod tck p 5 . 1 / tdi p 5 . 3 / tdo p 5 . 2 / tms sda / cs 0 scl / so - si p 5 . 0 / pfcgkill pfcpwm vss irmcf 311 ( top view ) fgatekill fpwmwl vac - vac + vaco ipfco ipfc + ipfc - ifbfo ifbf + ifbf - p 3 . 0 / int 2 / cs 1 cmext fpwmvh fpwmuh fpwmwh ain 1 p 3 . 2 / int 0 figure 3 . irmcf311 pin configuration
irmcf311 8 4 input/output of irmcf311 all i/o signals of irmcf311 are shown in figure 4 . all i/o pins are 3.3v logic interface except a/d interface pins . irmcf311 p1.1/rxd p1.2/txd p1.3/sync/sck p1.4/cap p3.0/int2/cs1 p5.1/tdi tck p5.2/tms cpwmuh cpwmul cpwmvh cpwmvl cpwmwh cpwmwl cgatekill ifbc+ ifbc- ifbco ain1 channel 1 pwm gate signal interface a/d interface discrete i/o jtag port p5.3/tdo communication interface xtal0 xtal1 crystal p2.6/aopwm0 d/a interface (pwm output) reset system reset avdd avss vdd1(3.3v) vdd2(1.8v) vss digital power/ ground tstmod test mode (must be tied vss) pllvdd pllvss pll power/ ground p2.7/aopwm1 aref ifbf+ ifbf- ifbfco vac+ vac- vaco ipfc+ ipfc- ipfco fpwmuh fpwmvh fpwmwh fgatekill channel 2 pwm gate signal interface pfcpwm p5.0/pgatekill power factor control pwm gate signal interface scl/sdi-sdo sda/cs0 p3.6/rxd1 p3.7/txd1 cmext ain0 fpwmul fpwmvl fpwmwl p3.2/int0 figure 4 . input/output of irmcf311 4.1 8051 peripheral interface group uart interface p1. 1/ rxd input, receive data to irmcf311
irmcf311 9 p1. 2/ txd output, transmit data from irmcf311 p 3.6/ rxd1 input, 2 nd channel receive data to irmcf311 p 3.7/ txd1 ou tput, 2 nd channel transmit data from irmcf311 discrete i/o interface p1.3 /sync/sck input/output port 1. 3, can be configured as sync output or spi clock, needs to be pulled up to vdd1 in order to boot from i 2 c eeprom p1.4 / cap input/output port 1. 4, can be configured as capture timer input p3.0/int2 /cs1 input/output port 3.0 , can be configured as external interrupt 2 or spi chip select 1 p3. 2 /int 0 input/output port 3. 2, can be configured as external interrupt 0 analog output interface p 2.6 /aopwm0 output , pwm output 0, 8- bit resolution, configurable carrier frequency p 2.7 /aopwm1 output , pwm output 1, 8- bit resolution, configurable carrier frequency crystal interface xtal0 input , connected to crystal xtal1 output, connected to crystal reset interface res et in out, system reset , needs to be pulled up to vdd1 but doesn?t require external rc time constant i 2 c/spi interface scl /s o - s i o utput , i 2 c clock output or spi data sda /cs0 input/o utput, i 2 c data line or spi c hip select 0 p3.0/int2/cs1 input/ o utput, int2 or spi chip select 1 p1.3/sync/sck input/ o utput, sync output or spi clock, needs to be pulled up to vdd1 in order boot from i 2 c eeprom 4.2 motion peripheral interface group pwm c pwmuh output, motor 1 pwm phase u high side gate signal c pwmul output, motor 1 pwm phase u low side gate signal c pwmvh output, motor 1 pwm phase v high side gate signal c pwmvl output, motor 1 pwm phase v low side gate signal c pwmwh output, motor 1 pwm phase w high side gate signal
irmcf311 10 c pwmwl output, motor 1 pwm phase w low side gate sig nal f pwmuh output, motor 2 pwm phase u high side gate signal f pwmul output, motor 2 pwm phase u low side gate signal f pwmvh output, motor 2 pwm phase v high side gate signal f pwmvl output, motor 2 pwm phase v low side gate signal f pwmwh output, motor 2 pwm phase w high side gate signal f pwmwl output, motor 2 pwm phase w low side gate signal pfcpwm output, pfc pwm fault c gatekill input, upon assertion, this negates all six pwm signals for motor 1 , programmable logic sense p5.0/ p fc gkill input, upon assertion , this negates pfc pwm signal , programmable logic sense , can be configured as discrete i/o in which case cgatekill negates pfcpwm f g ate kill input, upon assertion, this negates all six pwm signals for motor 2 , programmable logic sense 4.3 analog interface gro up a vdd analog power (1.8v) a vss analog power return aref buffered 0.6v output cmext unbuffered 0.6v, input to the aref buffer, capacitor needs to be connected. ifbc+ in put, operational amplifier positive input for shunt resistor current sensing of motor 1 ifbc - in put, operational amplifier negative input for shunt resistor current sensing of motor 1 ifbco out put, operational amplifier output for shunt resistor current sensing of motor 1 ifbf+ in put, operational amplifier positive input for shunt resistor current sensing of motor 2 ifbf - in put, operational amplifier negative input for shunt resistor current sensing of motor 2 ifbfo out put, operational amplifier output for shunt resistor current sensing of motor 2 ipfc+ in put, operational amplifier positive input for pfc current sensing ipfc - in put, operational amplifier negative input for pfc current sensing ipfo out put, operational amplifier output for pfc current sensing vac+ in put, operational amplifier positive input for pfc ac voltage sensing vac - in put , operational amplifier negative input for pfc ac voltage sensing vaco out put, operational amplifier output for pfc ac voltage sensing
irmcf311 11 ain0 input, analog input channel 0 (0 - 1.2v) , typically configured for dc bus voltage input ain1 input, analog input cha nnel 1 (0 - 1.2v ) , needs to be pulled down to avss if unused 4.4 power interface group vdd1 digital power for i/o (3.3v) vdd2 digital power for core logic (1.8v) vss d i gital common pllvdd pll power ( 1.8v) pllvss pll ground return 4.5 test interfac e group tst mod must be tied to vss, used only for factory testing. p5. 1 /td i input, jtag test data input , or programmable discrete i/o p5. 2 /tms input, jtag test mode select, or programmable discrete i/o t ck input, jtag test clock p5. 3/t do output, jtag test data output , or programmable discrete i/o
irmcf311 12 5 application connections typical application connection is shown figure 5. all components necessary to implement a complete sensorless drive control algorithm are shown connected to irmcf311. p 1.2/txd p1.1/rxd p1.3/sync/sck xtal0 cpwmuh cpwmul cpwmvh cpwmvl cpwmwh cpwmwl cgatekill ain1 to indoor unit microcontroller (rs232c) digital i/o control test mode system clock 4mhz crystal compressor igbt gate drive (i.e.irs2630d) compressor dc bus shunt resistor p2.6/aopwm 0 analog output xtal1 p1.4/cap p3.0/int2/cs 1 reset tstmod p5.1/tdi jtag control tck p5.2/tms p5.3/tdo 0.6v ifbc+ ifbc- ifbco other analog input (0-1.2v) avdd 1.8v avss vdd1 3.3v vdd2 1.8v vss cmext fpwmuh fpwmvh fpwmwh fgatekill fan motor igbt gate drive (i.e.ir21366) pfc igbt gate drive pgatekill pfcpwm fan motor dc bus shunt resistor 0.6v ifbf+ ifbf- ifbfo 0.6v ifbp+ ifbp- ifbpo fan motor dc bus shunt resistor vac+ vac- vaco ac line voltage optional external voltage reference (0.6v) p2.7/aopwm1 pllvdd 1.8v pllvss scl/sdi-sdo sda/cs0 other communication (i 2 c) pll logic rs232c i 2 c port1 port3 reset test mode circuit pwm0 pwm1 jtag interface low loss space vector pwm low loss space vector pwm pfc pwm s/h s/h s/h 8051 cpu dual port memory (1kbyte) & mce memory (3kbyte) motion control modules motion control sequencer 12bit a/d & mux system clock local ram 4kbyte program ram (48kbyte) system reset watchdog timer timer irmcf311 rs232c p3.7/txd p3.6/rxd to other host (rs232c) dc bus voltage aref ain0 fpwmul fpwmvl fpwmwl 3.3v figure 5 . application connection of irmcf311
irmcf311 13 6 dc characteristics 6.1 absolute maximum ratings symbol parameter min typ max condition v dd1 supply voltage - 0.3 v - 3.6 v respect to v ss v dd2 supply voltag e - 0.3 v - 1.98 v respect to v ss v i a analog input voltage - 0.3 v - 1.98 v respect to avss v id digital input voltage - 0.3 v - 3.65 v respect to v ss t a ambient temperature - 40 ? c - 85 ? c t s storage temperature - 65 ? c - 150 ? c table 1 . absolute maximum ratings caution : stresses beyond those listed in ?absolute maximum ratings? may cause permanent damage to the device. these are stress ratings only an d function of the device at these or any other conditions beyond those indicated in the operational sections of the specifications are not implied. 6.2 system clock frequency and power consumption symbol parameter min typ max unit sysclk s ystem clock 32 - 128 mhz table 2 . system clock frequency figure 6 . clock frequency vs . power consumption 0 40 80 120 160 200 240 0 50 100 150 clock frequency (mhz) power (mw) vdd2 (1.8v) vdd1 (3.3v) total
irmcf311 14 6.3 digital i/o dc characteristics symbol parameter min typ max condition v dd1 supply voltage 3 .0 v 3.3 v 3.6 v re commended v dd2 supply voltage 1.62 v 1.8 v 1.98 v re commended v il input low voltage - 0.3 v - 0.8 v re commended v ih input high voltage 2.0 v 3 . 6 v re commended c in input capacitance - 3.6 p f - ( 1 ) i l input leakage current 10 na 1 a v o = 3.3 v or 0 v i ol1 ( 2 ) low level output current 8.9 ma 13.2 ma 15.2 ma v ol = 0.4 v ( 1 ) i oh1 ( 2 ) high level output current 12.4 ma 24.8 ma 38 ma v oh = 2.4 v ( 1 ) i ol2 ( 3 ) low level output current 17.9 ma 26.3 ma 33.4 ma v ol = 0.4 v ( 1 ) i oh2 ( 3 ) high l evel output current 24.6 ma 49.5 ma 81 ma v oh = 2.4 v ( 1 ) table 3 . digital i/o dc characteristics note: (1) data guaranteed by design. (2) applied to scl/so - si, sda/cs0 pins. (3) applied to p1.1/r xd , p1.2/ txd, p1 . 3/sync /sck , p1 .4/ cap , p2 .6/ aopwm0 , p2 .7 /aopwm1 , p3.0/int2/cs1, p3.2/int0, p3.6/rxd1, p3. 7/ t xd1, p5.0/pfcgkill, p5. 2 /tms, p5.3 /tdo, p5.1/ t di, cgatekill, fgatekill , cpwmul, cpwmuh, cpwmvl, cpwmvh, cpwmwl, cpwmwh, fpwmul, fpwmuh, fpwmvl, fpwmvh, fpwmwl, fpwmwh, and pfcpwm pins.
irmcf311 15 6.4 pll and oscillator dc c haracteristics symbol parameter min typ max condition v pllvdd supply voltage 1.62 v 1.8 v 1.92 v recommended v il osc oscillator input low voltage v pllvss - 0.2* v pllvdd v pllvdd = 1.8 v ( 1 ) v ih osc oscillator input high voltage 0.8* v pllvdd v pllvdd v pllvdd = 1.8 v ( 1 ) table 4 . pll dc characteristics note: (1) data guaranteed by design. 6.5 analog i/o dc c haracteristics - op amps for current sensing (ifbc+, ifbc - , ifbco, ifbf+, ifbf - , ifbfo, ipfc+, ipfc - , ipfco) c aref = 1nf, c mext = 100nf. unless specified, ta = 25 ? c . symbol parameter min typ max condition v avdd supply voltage 1.71 v 1.8 v 1.89 v recommended v offset input offset voltage - - 26 mv v avdd = 1.8 v v i input voltage range 0 v 1.2 v recommended v ou tsw op amp output operating range 50 mv ( 1 ) - 1.2 v v avdd = 1.8 v c in input capacitance - 3.6 p f - ( 1 ) r fdbk op amp feedback resistor 5 k ? - 20 k ? requested b etween op am p output and negative input op gaincl operating close loop gain 80 db - - ( 1 ) cmr r common mode rejection ratio - 80 db - ( 1 ) i src op amp output source current - 1 ma - v out = 0.6 v ( 1 ) i snk op amp output sink current - 100 a - v out = 0.6 v ( 1 ) table 5 . analog i/o dc characteristics note: ( 1) data guaranteed by design.
irmcf311 16 6.6 analog i/o dc c haracteristics - op amp for voltage sensing (vac+,vac - ,vaco) c aref = 1nf, c mext = 100nf. u nless specified , ta = 2 5? c . symbol parameter min typ max condition v avdd supply voltage 1.71 v 1.8 v 1.89 v v offset input offset voltage - - 26 mv v avdd = 1.8 v v i input voltage range 0 v 1.2 v v outsw op amp output operating range 50 mv ( 1 ) - 1.2 v v avdd = 1.8 v c in inpu t capacitance - 3.6 p f - ( 1 ) op gaincl operating close loop gain 80 db - - ( 1 ) cmrr common mode rejection ratio - 80 db - ( 1 ) i src op amp output source current - 5 ma - v out = 0.6 v ( 1 ) i snk op amp output sink current - 500 a - v out = 0.6 v ( 1 ) tabl e 6 . analog i/o dc characteristics note: (1) data guaranteed by design .
irmcf311 17 6.7 under voltage lockout dc c haracteristics - based on avdd (1.8v) unless specified, ta = 25 ? c . symbol parameter min typ max condition u v cc+ uvcc positive going threshold 1.53 v 1.6 6 v 1.71 v v dd1 = 3.3 v u v cc- uvcc negative going threshold 1.52 v 1.6 2 v 1.71 v v dd1 = 3.3 v u v cc h uvcc hysteresys - 40 mv - table 7 . uvcc dc characteristics 6.8 cmext and aref chara cteristics c aref = 1n f, c mext = 100nf. unless specified, ta = 25 ? c . symbol parameter min typ max condition v cm cmext voltage 495 mv 600 mv 700 mv v avdd = 1.8 v v aref buffer output voltage 495 mv 600 mv 700 mv v avdd = 1.8 v ? v o load regulation (v dc - 0.6) - 1 mv - ( 1 ) psrr power supply rejection ratio - 75 db - ( 1 ) t able 8 . cmext and aref dc characteristics note: (1) data guaranteed by design .
irmcf311 18 7 ac c haracteristics 7.1 pll ac c haracteristics symbol parameter min typ max condition f clki n crystal i nput frequency 3.2 mhz 4 mhz 60 mhz ( 1 ) (see figure below) f pll internal clock frequency 32 mhz 50 mhz 128 mhz ( 1 ) f lwpw sleep mode o utput frequency f clki n 256 - - ( 1 ) j s short time jitter - 200 psec - ( 1 ) d duty cycle - 50 % - ( 1 ) t lock pll lock time - - 500 sec ( 1 ) table 9 . pll ac characteristics note: ( 1) data guaranteed by design. xtal r 1 =1m r 2 =10 c 1 =30pf c 2 = 30pf
irmcf311 19 7.2 analog to digital converter ac c haracteristics unless specified, ta = 2 5? c . symbol parameter min typ ma x condition t conv conversion time - - 2.05 sec ( 1 ) t hold sample/hold maximum hold time - - 10 sec voltage droop 15 lsb (see figure below) table 10. a/d converter ac characteristics note: ( 1) data guaranteed by design. t hold voltage droop t sample s/h voltage input voltage
irmcf311 20 7.3 op amp ac characteristics - op amps for current sensing (ifbc+, ifbc - , ifbco, ifbf+, ifbf - , ifbfo, ipfc+, ipfc - , ipfco) unless specified, ta = 2 5? c . symbol parameter min typ max condition op sr op amp slew rate - 10 v/ se c - v avdd = 1.8 v, cl = 33 p f ( 1 ) op imp op input impedance - 10 8 - ( 1 ) t set settling time - 400 ns - v avdd = 1.8 v, cl = 33 p f ( 1 ) table 11. current sensing op amp ac characteristics note: ( 1) data guaranteed by design. 7.4 o p amp ac c haracteristics - op amp for voltage sensing (vac+,vac - ,vaco) unless specified, ta = 2 5? c . symbol parameter min typ max condition op sr op amp slew rate 2.5 v/ sec - v avdd = 1.8 v, cl = 33 p f ( 1 ) op imp op input impedance - 10 8 - ( 1 ) t set se ttling time 650 ns v avdd = 1.8 v, cl = 33 p f ( 1 ) table 12. voltage sensing op amp ac characteristics note: ( 1) data guaranteed by design.
irmcf311 21 7.5 sync to svpwm and a/d conversion ac t iming sync iu, iv, iw t wsync t dsync1 ainx t dsync2 pwmux,pwmvx,pwmwx t dsync3 unless speci fied, ta = 2 5? c . symbol parameter min typ max unit t w sync sync pulse width - 32 - sysclk t dsync1 sync to current feedback conversion time - - 100 sysclk t dsync2 sync to ain0 - 6 analog input conversion time - - 200 sysclk ( 1 ) t dsync3 sync to pwm output delay time - - 2 sysclk table 13. sync ac characteristics note: ( 1) ain 1 through ain6 channels are converted once every 6 sync events
irmcf311 22 7.6 gatekill to svpwm ac t iming gatekill pwmux , pwmvx , pwmwx t w gk t d gk unless specified, ta = 2 5? c . symbol parame ter min typ max unit t w gk gatekill pulse width 32 - - sysclk t dgk gatekill to pwm output delay - - 100 sysclk table 14. gatekill to svpwm ac timing 7.7 i nterrupt ac t iming p 3 . 2 / int 0 p 3 . 3 / int 1 internal program counter internal vector fetch t w int t di nt unless specified, ta = 25? c . symbol parameter min typ max unit t w int int0, int1 interrupt assertion time 4 - - sysclk t di nt int0, int1 latency - - 4 sysclk table 15. interrupt ac timing
irmcf311 23 7.8 i 2 c ac t iming scl sda t i 2 st 1 t i 2 st 2 t i 2 wsetup t i 2 clk t i 2 whold t i 2 rsetup t i 2 rhold t i 2 clk t i 2 en 1 t i 2 en 2 unless speci fied, ta = 2 5? c . symbol parameter min typ max unit t i2clk i 2 c clock period 10 - 8192 sysclk t i2st1 i 2 c sda start time 0.25 - - t i2clk t i2st2 i 2 c scl start time 0.25 - - t i2clk t i2wsetup i 2 c write setup time 0.25 - - t i2clk t i2whold i 2 c write hold tim e 0.25 - - t i2clk t i2rsetup i 2 c read setup time i 2 c filter time ( 1 ) - - sysclk t i2rhold i 2 c read hold time 1 - - sysclk table 16. i 2 c ac timing note: ( 1) i 2 c read setup time is determined by the programmable filter time applied to i 2 c communication.
irmcf311 24 7.9 spi ac timing 7.9.1 spi write ac timing p 1 . 3 / sync / sck scl / s o - s i t spiclk t wrdelay t cshold sda / cs 0 p 3 . 0 / int 2 / cs 1 t cshigh bit 7 ( msb ) bit 0 ( lsb ) t spiclkht t spiclklt t csdelay unless specified, ta = 2 5? c . symbol parameter min typ max unit t spiclk spi clock period 4 - - sysclk t spiclkht spi clock high time - 1/2 - t spiclk t spiclklt spi clock low time - 1/2 - t spiclk t csdelay cs to data delay time - - 10 nsec t wrdelay clk falling edge to data delay time - - 10 nsec t cshigh cs hi gh time between two consecutive byte transfer 1 - - t spiclk t cshold cs hold time - 1 - t spiclk table 17. spi write ac timing
irmcf311 25 7.9.2 spi read ac timing p 1 . 3 / sync / sck scl / s o - s i t spiclk t rdsu t cshold sda / cs 0 p 3 . 0 / int 2 / cs 1 t cshigh bit 7 ( msb ) bit 0 ( lsb ) t spiclkht t spiclklt t csrd t rdhold unless specified, ta = 2 5? c . symbol parameter min typ max unit t spiclk spi clock period 4 - - sysclk t spiclkht spi clock high time - 1/2 - t spiclk t spiclklt spi clock low time - 1/2 - t spiclk t csrd cs to data delay time - - 10 nsec t rdsu spi read data setup time 10 - - nsec t rdhold spi read data hold time 10 - - nsec t cshigh cs hi gh time between two consecutive byte transfer 1 - - t spiclk t cshold cs hold time - 1 - t spiclk table 18. spi read ac timing
irmcf311 26 7.10 uart ac t iming txd rxd data and parity bit start bit t baud stop bit t uartfil unless specified, ta = 2 5? c . symbol parameter min typ max unit t baud baud rate period - 576 00 - bit/sec t uartfil uart sampling filter period ( 1 ) - 1/16 - t baud table 19. uart ac timing note: ( 1) each bit including start and stop bit is sampled three t imes at center of a bit at an interval of 1/16 t baud . if three sampled values do not agree, then uart noise error is generated.
irmcf311 27 7.11 capture i nput ac t iming p1.4/cap crev(h,l) internal register t caphigh t capclk t crdelay t caplow t cldelay clast(h,l) internal register t intdelay interrupt vector fetch interrupt unless specified, ta = 2 5? c . symbol parameter min typ max unit t capc lk capture input period 8 - - sysclk t caphigh capture input high time 4 - - sysclk t caplow capture input low time 4 - - sysclk t crdelay capture falling edge to capture register latch time - - 4 sysclk t cldelay capture rising edge to capture regis ter latch time - - 4 sysclk t intdelay capture input interrupt latency time - - 4 sysclk table 20. capture ac timing
irmcf311 28 7.12 jtag ac t iming tck tdo t jhigh t jclk t co t jlow t jsetup t jhold tdi/tms unless specified, ta = 2 5? c . symbol parameter min typ max unit t jclk tck period - - 50 mhz t jhigh tck high period 10 - - nsec t jlow tck low period 10 - - nsec t co tck to tdo propagation delay time 0 - 5 nsec t jsetup tdi/tms setup time 4 - - nsec t jhold tdi/tms hold time 0 - - nsec table 21. jtag ac timing
irmcf311 29 8 i/o structure the following figure shows the pwm and digital i/o struc ture. 6 . 0 v 6 . 0 v internal digital circuit low true logic vdd 1 ( 3 . 3 v ) 70 k ? pin 270 ? figure 7 all digital i/o and pwm output s the following fi gure shows reset and gatekill i/o structure. 270 ? 6.0v 6.0v reset gatekill circuit vdd1 (3.3v) 70k ? pin vss figure 8 reset, gatekill i/o
irmcf311 30 the following figure shows the analog input structure. 1 ? 6.0v 6.0v analog input pin avss analog circuit avdd figure 9 analog input the following figure shows all analog operational amplifi er output pins and aref pin i/o structure. 6.0v 6.0v analog output pin avss analog circuit avdd figure 10 analog operational amplifier output and aref i/o structure the following figure shows the vss , avss and pllvss pin structure pin vdd1 avdd pllvdd 6.0v figure 11 vss, avss and pllvss pin structure the foll owing figure shows the vdd1, vdd2 , avdd and pllvdd pin structure
irmcf311 31 pin vss avss pllvss 6.0v figure 12 vdd1, vdd2, avdd and pllvdd pin structure the following figure shows the xtal0 and xtal1 pins structure 1 ? 6.0v 6.0v pin pllvdd pllvss figure 13 xtal0/xtal1 pins structure
irmcf311 32 9 pin li st pin number pin name internal ic pull - up /pull - down pin type description 1 xtal0 i crystal input 2 xtal1 o crystal output 3 p1 .1 / rxd 70 k pull up i/o discrete programmable i/o or uart receive input 4 p1.2/txd 70 k pull up i/ o discrete programm able i/o or uart transmit output 5 p1.3/sync / sck 70 k pull up i /o discrete programmable i/o or sync out put or spi clock , needs to be pulled up to vdd1 in order to boot from i 2 c eeprom 6 p1.4/cap 70 k pull up i/ o discrete programmable i/o or capture ti mer in put 7 vdd2 p 1.8v digital power 8 vss p d igital common 9 vdd1 p 3.3v digital power 10 fgatekill 70 k pull up i fan pwm shutdown input, 2 - sec digital filter, c onfigurable either high or low true. 11 fpwm wl 70 k pull up o fan pwm gate dri ve for phase w low side , c onfigurable either high or low true 12 fpwmwh 70 k pull up o fan pwm gate drive for phase w high side , c onfigurable either high or low true 13 fpwmv l 70 k pull up o fan pwm gate drive for phase v low side , c onfigurable either high or low true 14 fpwmv h 70 k pull up o fan pwm gate drive for phase v high side , c onfigurable either high or low true 15 fpwmul 70 k pull up o fan pwm gate drive for phase u low side , c onfigurable either high or low true 16 fpwmu h 70 k pull up o f an pwm gate drive for phase u high side , c onfigurable either high or low true 1 7 p2 .6/ aopwm0 70 k pull up i/ o discrete programmable i/o or analog output 0 (pwm) 18 p2.7/ aopwm1 70 k pull up discrete programmable i/o or analog output 1 (pwm) 1 9 vdd2 p 1.8v digital power 20 vss p digital common 21 ifbf - i fan single shunt current sensing op amp input ( - ) 22 ifbf+ i fan single shunt current sensing op amp input (+) 23 ifbfo o fan single shunt current sensing op amp output
irmcf311 33 pin number pin name internal ic pull - up /pull - down pin type description 24 ain 0 i analog inp ut channel 0 , 0 - 1.2v range , needs to be pulled down to avss if unused 25 avdd p 1.8v analog power 26 avss p analog common 2 7 ain1 i analog input channel 1, 0 - 1.2v range , needs to be pulled down to avss if unused 28 cmext o unbuffered a n alog reference voltage output (0.6v) , capacitor needs to be connected. 29 aref o a nalog reference voltage output (0.6v) 30 ifbc - i compressor single shunt current sensing op amp input ( - ) 3 1 ifbc+ i compressor single shunt current sensing op amp input (+) 3 2 ifbco o compressor single shunt current sensing op amp output 3 3 vac - i ac input voltage sensing op amp input ( - ) 3 4 vac+ i ac input voltage sensing op amp input (+) 3 5 vaco o ac input voltage sensing op amp output 3 6 i pfco o pfc shunt current sensing op amp output 3 7 ipfc+ i pfc shunt current sensing op amp input (+) 3 8 ipfc - i pfc shunt current sensing op amp input ( - ) 3 9 vss p d igital common 40 vdd1 p 3.3v digital power 4 1 cgatekill 70 k pull up i compress or pwm shutdown input, 2 - sec digital filter, c onfigurable either high or low true. 42 c pwm wl 70 k pull up o compressor pwm gate drive for phase w low side , c onfigurable either high or low true 43 c pwmwh 70 k pull up o compressor pwm gate drive for p hase w high side , c onfigurable either high or low true 44 c pwmv l 70 k pull up o compressor pwm gate drive for phase v low side , c onfigurable either high or low true 45 c pwmv h 70 k pull up o compressor pwm gate drive for phase v high side , c onfigurable either high or low true 46 c pwmul 70 k pull up o compressor pwm gate drive for phase u low side , c onfigurable either high or low true 47 c pwmu h 70 k pull up o compressor pwm gate drive for phase u high side , c onfigurable either high or low true 4 8 p 3. 0 / int2 70 k pull up i/o discrete programmable i/o or int2 digital in put
irmcf311 34 pin number pin name internal ic pull - up /pull - down pin type description 49 p5.0/ p fc gkill 70 k pull up i discrete programmable i/o or pfc pwm shutdown input, 2- sec digital filter, c onfigurable either high or low true. 5 0 pfcpwm 70 k pull up o pfc p wm gate drive , c onfigurable either high or low true 51 p 3. 2/ int 0 70 k pull up i/o discrete programmable i/o or int 0 in put 5 2 p 3.6 / rxd1 70 k pull up i/o discrete programmable i/o or 2 nd uart receive input 5 3 p3.7/txd1 70 k pull up i/ o discrete program mable i/o or 2 nd uart transmit output 54 vss p d igital common 55 scl/s o - s i 70 k pull up i/o i 2 c clock output or spi data 56 sda/cs0 70 k pull up i/ o i 2 c data or spi chip select 0 57 p5. 2 /tms 70 k pull up i/o discrete programmable i/o or jtag test m ode select 58 p5. 3 /tdo 70 k pull up i/o discrete programmable i/o or jtag port test data output 59 p5. 1 /tdi 70 k pull up i/o discrete programmable i/o or jtag test data input 60 tck i jtag test cl oc k 61 tstmod 58 k pull down i test mode. must be ti ed to vss. factory use only 62 reset 70 k pull up i /o reset , low true, schmitt trigger input 63 pllvdd p 1.8 v pll power 64 pllvss p pll ground table 22 . pin list
irmcf311 this document is the property of international rectifier and may not be copied or distributed without expressed consent. 10 package dimensions
irmcf311 36 11 part marking information irmcf 311 ywwp xxxxxx ir logo production lot date code part number pin 1 indentifier order information lead - free part in 64 - lead qfp moisture sensitivity rating ? msl3 part number order quantities irmcf311tr 1500 parts on tape and reel in dry pack irmcf311ty 1600 part s on trays (160 parts per tray) in dry pack the lqfp - 64 is msl3 qualified this product has been designed and qualified for the industrial level qualification standards can be found at www.irf.com ir world headquarters: 233 kansas st., el segundo, california 90245, tel: (310) 252 - 7105 data and specifications subject to change without notice. 1 2 / 05 /2006 www.irf.com

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